The methods of the invention can be applied to any block-based structure or system, whose safety, performance and life expectancy are strongly influenced by temperature, in different fields of technology. Only semiconductor chips and battery packs are described in this section.
High temperatures in semiconductor chips caused by heating in individual devices and interconnects have a significant impact on chip performance and reliability. Designers of integrated circuits (ICs) and systems must consider power and thermal management issues to improve performance and reliability. Semiconductor chips typically consist of a large number of devices and interconnects and the number of devices in high performance chips have been growing rapidly to meet increasing demands for sophisticated functions and computational performance. The large number of devices and long interconnect lines between devices, cells, and circuit blocks inevitably induce heating problems. This has become one of the major obstacles to accomplishing cost-effective design of ICs and systems in the semiconductor industry, including not only the conventional digital, analog, RF, and mixed signal CMOS (complementary metal-oxide-semiconductor) technologies but also many other semiconductor technologies, such as BiCMOS (bipolar CMOS), SOI (Silicon-On-Insulator), Bipolar, MMIC (Monolithic Microwave and Millimeter wave IC), and photonic ICs, etc.
FIG. 1 illustrates an example of a silicon IC structure (a silicon chip) 100 that includes two bulk MOS devices 102a and 102b and the first to fourth layer interconnects (metal wires M1-M4) 104a-104d. The metal contacts 106 connect the device terminals to M1 104a, and vias 108 make connections between metal wires from one interconnect layer to another. The devices, as well as the metal wires and vias, dissipate power and therefore induce thermal heating. In addition, heat exchange between devices and metal wires also has an effect on the electronic performance of the chip. Another example of an silicon IC structure 200 based on SOI technology is illustrated in FIG. 2, where on the first silicon island there is only one SOI MOS device 202a but 2 SOI MOS devices 202b and 202c on the second one. Similarly to the structure 100, the devices 202a-202c, the interconnect layers (metal wires M1-M4) 204a-204d, the metal contacts 206, and the vias 208 dissipate power and induce thermal heating. Multi-finger structures are also possible but not included in FIG. 1 or 2. Number of the metal layers may vary depending on the complexity and the numbers of devices in the chips.
Other semiconductor IC technologies may have different device and/or layout structures; however, thermal gradients and heat exchange between devices and interconnects are inevitable and become more serious as the numbers of devices and interconnects in a chip increase.
To increase performance, devices and interconnects in semiconductor chips are being scaled down, which leads to a reduction in design thermal margins. This then results in the need for more accurate and efficient thermal simulations at the device, interconnect and package levels as the power consumption and delays are strongly influenced by the local temperature distributions in a chip. It is important for chip designers to predict the local temperatures in devices and circuits and to consider the temperature effects at every stage of the design flow. The evaluated temperatures can then be used as a guideline to achieve thermal aware and cost-effective chip designs. The detailed temperature information in the chip can offer more meaningful reliability analysis as well. For example, based on the predicted temperature distribution in a chip, it may be necessary to change the placement and routing of devices and/or interconnects in the chip to avoid generating hot spots that may overheat the chip and trigger a failure. To accomplish this, an efficient simulation tool for detailed steady-state and transient temperature analysis for semiconductor chip design is essential.
It should be mentioned that the miniaturization of devices into nano-scale dimensions also enhances two major problems in semiconductor industry: pronounced short channel effects in the traditional bulk CMOS technology and long interconnect lines in the conventional planar IC structure. The former gives rise to large leakage power and the channel punch-through characteristics in CMOS devices, and the latter induces long interconnect delays and high power consumption along the long interconnects.
To diminish the short channel effects, SOI (Silicon-on-Insulator) technology has been proposed and successfully implemented in the chip industry. The SOI-based technology however considerably increases self-heating effects because the oxide placed under the device channels to suppress the short-channel effects exacerbates the chip heating problem. To minimize the interconnect delays, 3D stacked packaging architectures have been investigated in recent years. These technologies place the conventional planar circuit blocks or dies vertically to reduce the interconnect lengths and delays but worsens the chip heating problem due to the increase in power density and the difficulty to dissipate heat to the ambient. There have been various approaches to 3D stacking technologies. Some of proposed stacking structures are able to integrate different technologies together, such as CMOS, photonics, MEMs (Micro-Electro-Mechanical Systems), and MMIC technologies, etc.
As the semiconductor technology moves into the nanoscale and 3D-integration structures, chip heating is becoming more serious, and temperature effects on chip performance, reliability, and power and thermal management for design of semiconductor chips and packages are enhanced. Therefore, the need for a method to achieve more efficient and accurate full-chip and full-scale thermal simulation will increase for semiconductor chip design.
Currently, there exist many methods for thermal simulation and analysis in semiconductor chip design. Evaluation of the detailed thermal profiles in semiconductor chips relies on full-scale numerical simulation based on finite element or finite difference methods. These approaches are however computationally time consuming and difficult to use to achieve cost-effective design. For efficient thermal simulation, compact (or lumped) thermal models are usually used. These approaches require assumptions related to heat dissipation paths, temperature profiles, geometry and/or the thermal elements (thermal resistors and capacitors) that are usually modeled by effective dimensions or effective thermal conductivities extracted from simulations or experiments. These approximations may not provide accurate heat flow or heat exchange between devices and/or interconnects in complex multi-dimensional IC geometry. In addition, they are not able to capture high temperature gradients or hot spots in chips.
Thus, there is a need for a method, which is able to offer the temperature profile in a semiconductor chip as detailed as a full-scale numerical simulation with computational time comparable to that of a compact thermal model, for full-chip thermal simulation and analysis in semiconductor chip design.
Furthermore, for electronic IC design, capability of implementing the 3D thermal model in a circuit simulator (e.g., SPICE or other circuit simulators) for efficient electro-thermal simulation of ICs is desirable to be able to predict the local runtime temperatures of devices and interconnects. Such capability will allow chip designers to have access to runtime device and interconnect temperature distributions, including the hot spots in the chips, to accurately take into account runtime thermal effects for a more successful thermally-aware chip design.
The methods of the invention are also idea approaches to thermal simulation of the battery pack which stacks many battery cells or units to achieve the desired electric performance. Battery technology has great influence on many applications, including portable electronics, computers, electric and hybrid electric vehicles, space and aircraft power systems, etc. The internal temperature distributions in stacked battery cells significantly affect performance and reliability of the battery pack. It is necessary to take into account the uneven temperature heating and cooling and non-uniform power flow inside the battery pack to account for the influence of temperature variations over the battery cells. The parameters of the electric elements in the electrochemical model of each cell are in general strongly dependent on local temperature. The non-uniform temperature distribution in the battery pack will thus lead to unbalanced cell impedances and power flow, lower performance and shorter life expectancy. For some batteries, high cell temperature may also induce thermal runaway and cause safety problems. Knowledge of 3D temperature profiles inside the battery pack is therefore crucial not only for optimal battery design but also for optimal battery operation. Consequently, thermal management in the battery and automotive industries has become one of the major issues for optimizing battery operation, performance, safety and life expectancy.
The detailed temperature profiles in the battery packs are currently derived from numerical thermal simulation, which is very time consuming especially in the dynamic cases. To account for temperature influences on the electrochemical model of each battery cell, it needs to couple the numerical thermal simulation with the electrochemical model, which substantially increases the simulation time and is prohibitive for realistic applications. As a result, constant cell temperature is usually assumed to simplify the simulation, which however does not reflect the realistic heat generation, local temperature effects on element parameters of the battery cell electrochemical model, and the heat flow across cells. A considerably more efficient thermal approach, which is able to provide the temperature profile in the battery pack as detailed as a full-scale numerical simulation, will be very useful for electrochemical-thermal simulation to take into account thermal effects for achieving optimal battery design and operation.